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初版适配和修改

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cyy_mac
2026-08-07 19:04:38 +08:00
parent 460e0e9e73
commit f695460797
17 changed files with 1701 additions and 1 deletions
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.gitignore vendored Normal file
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build/
.DS_Store

30
.vscode/c_cpp_properties.json vendored Normal file
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{
"configurations": [
{
"name": "STM32F407ZG (ARM GCC)",
"includePath": [
"${workspaceFolder}/GCC_COMPAT/include",
"${workspaceFolder}/USER",
"${workspaceFolder}/CORE",
"${workspaceFolder}/FWLIB/inc",
"${workspaceFolder}/SYSTEM/**",
"${workspaceFolder}/HARDWARE/**",
"${workspaceFolder}/BALANCE",
"${workspaceFolder}/FreeRTOS/include",
"${workspaceFolder}/FreeRTOS/portable/GCC/ARM_CM4F"
],
"defines": [
"STM32F40_41xxx",
"USE_STDPERIPH_DRIVER",
"ARM_MATH_CM4",
"HSE_VALUE=8000000U",
"__FPU_PRESENT=1",
"__FPU_USED=1"
],
"compilerPath": "/opt/homebrew/bin/arm-none-eabi-gcc",
"cStandard": "c11",
"intelliSenseMode": "linux-gcc-arm"
}
],
"version": 4
}

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.vscode/launch.json vendored Normal file
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{
"version": "0.2.0",
"configurations": [
{
"name": "DAPLink Debug",
"cwd": "${workspaceFolder}",
"executable": "${workspaceFolder}/build/debug/OriginCar.elf",
"request": "launch",
"type": "cortex-debug",
"device": "STM32F407ZG",
"svdFile": "${workspaceFolder}/../../stm32/stm32f407-gcc-framework/STM32F407.svd",
"servertype": "openocd",
"configFiles": ["${workspaceFolder}/openocd.cfg"],
"preLaunchTask": "Build Debug",
"runToEntryPoint": "main",
"overrideLaunchCommands": [
"monitor reset init",
"load",
"monitor reset init"
],
"liveWatch": { "enabled": true, "samplesPerSecond": 4 }
},
{
"name": "DAPLink Attach",
"cwd": "${workspaceFolder}",
"executable": "${workspaceFolder}/build/debug/OriginCar.elf",
"request": "attach",
"type": "cortex-debug",
"device": "STM32F407ZG",
"svdFile": "${workspaceFolder}/../../stm32/stm32f407-gcc-framework/STM32F407.svd",
"servertype": "openocd",
"configFiles": ["${workspaceFolder}/openocd.cfg"],
"liveWatch": { "enabled": true, "samplesPerSecond": 4 }
}
]
}

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.vscode/settings.json vendored Normal file
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{
"cortex-debug.armToolchainPath": "/opt/homebrew/bin",
"cortex-debug.openocdPath": "/opt/homebrew/bin/openocd",
"cortex-debug.armToolchainPrefix": "arm-none-eabi",
"cortex-debug.variableUseNaturalFormat": true
}

22
.vscode/tasks.json vendored Normal file
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{
"version": "2.0.0",
"tasks": [
{
"label": "Build Debug",
"type": "shell",
"command": "make",
"args": ["-j8", "BUILD=debug", "all"],
"options": { "cwd": "${workspaceFolder}" },
"group": { "kind": "build", "isDefault": true },
"problemMatcher": ["$gcc"]
},
{
"label": "Flash DAPLink",
"type": "shell",
"command": "make",
"args": ["BUILD=debug", "flash"],
"options": { "cwd": "${workspaceFolder}" },
"problemMatcher": []
}
]
}

763
FreeRTOS/portable/GCC/ARM_CM4F/port.c Normal file
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/*
FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the ARM CM4F port.
*----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#ifndef __VFP_FP__
#error This port can only be used when the project options are configured to enable hardware floating point support.
#endif
#ifndef configSYSTICK_CLOCK_HZ
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
/* Ensure the SysTick is clocked at the same frequency as the core. */
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#else
/* The way the SysTick is clocked is not modified in case it is not the same
as the core. */
#define portNVIC_SYSTICK_CLK_BIT ( 0 )
#endif
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
r0p1 port. */
#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
#define portPRIGROUP_SHIFT ( 8UL )
/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
#define portVECTACTIVE_MASK ( 0xFFUL )
/* Constants required to manipulate the VFP. */
#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
/* Constants required to set up the initial stack. */
#define portINITIAL_XPSR ( 0x01000000 )
#define portINITIAL_EXEC_RETURN ( 0xfffffffd )
/* The systick is a 24-bit counter. */
#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
/* For strict compliance with the Cortex-M spec the task start address should
have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
/* A fiddle factor to estimate the number of SysTick counts that would have
occurred while the SysTick counter is stopped during tickless idle
calculations. */
#define portMISSED_COUNTS_FACTOR ( 45UL )
/* Let the user override the pre-loading of the initial LR with the address of
prvTaskExitError() in case it messes up unwinding of the stack in the
debugger. */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
#define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/* Each task maintains its own interrupt status in the critical nesting
variable. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
* generate the tick interrupt.
*/
void vPortSetupTimerInterrupt( void );
/*
* Exception handlers.
*/
void xPortPendSVHandler( void ) __attribute__ (( naked ));
void xPortSysTickHandler( void );
void vPortSVCHandler( void ) __attribute__ (( naked ));
/*
* Start first task is a separate function so it can be tested in isolation.
*/
static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
/*
* Function to enable the VFP.
*/
static void vPortEnableVFP( void ) __attribute__ (( naked ));
/*
* Used to catch tasks that attempt to return from their implementing function.
*/
static void prvTaskExitError( void );
/*-----------------------------------------------------------*/
/*
* The number of SysTick increments that make up one tick period.
*/
#if configUSE_TICKLESS_IDLE == 1
static uint32_t ulTimerCountsForOneTick = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
* The maximum number of tick periods that can be suppressed is limited by the
* 24 bit resolution of the SysTick timer.
*/
#if configUSE_TICKLESS_IDLE == 1
static uint32_t xMaximumPossibleSuppressedTicks = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
* Compensate for the CPU cycles that pass while the SysTick is stopped (low
* power functionality only.
*/
#if configUSE_TICKLESS_IDLE == 1
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
#if ( configASSERT_DEFINED == 1 )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED */
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
/* Offset added to account for the way the MCU uses the stack on entry/exit
of interrupts, and to ensure alignment. */
pxTopOfStack--;
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
/* Save code space by skipping register initialisation. */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXEC_RETURN;
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
/* A function that implements a task must not exit or attempt to return to
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
portDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
__asm volatile (
" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
" ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
" msr psp, r0 \n" /* Restore the task stack pointer. */
" isb \n"
" mov r0, #0 \n"
" msr basepri, r0 \n"
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
/*-----------------------------------------------------------*/
static void prvPortStartFirstTask( void )
{
__asm volatile(
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n"
" ldr r0, [r0] \n"
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
" cpsie i \n" /* Globally enable interrupts. */
" cpsie f \n"
" dsb \n"
" isb \n"
" svc 0 \n" /* System call to start first task. */
" nop \n"
);
}
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
/* This port can be used on all revisions of the Cortex-M7 core other than
the r0p1 parts. r0p1 parts should use the port from the
/source/portable/GCC/ARM_CM7/r0p1 directory. */
configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
#if( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
functions can be called. ISR safe functions are those that end in
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
ensure interrupt entry is as fast and simple as possible.
Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to all
possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
/* Calculate the maximum acceptable priority group value for the number
of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulMaxPRIGROUPValue--;
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
/* Restore the clobbered interrupt priority register to its original
value. */
*pucFirstUserPriorityRegister = ulOriginalPriority;
}
#endif /* conifgASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
vPortSetupTimerInterrupt();
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
/* Start the first task. */
prvPortStartFirstTask();
/* Should never get here as the tasks will now be executing! Call the task
exit error function to prevent compiler warnings about a static function
not being called in the case that the application writer overrides this
functionality by defining configTASK_RETURN_ADDRESS. */
prvTaskExitError();
/* Should not get here! */
return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
Artificially force an assert. */
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
}
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
configASSERT( uxCriticalNesting );
uxCriticalNesting--;
if( uxCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
}
}
/*-----------------------------------------------------------*/
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
(
" mrs r0, psp \n"
" isb \n"
" \n"
" ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
" ldr r2, [r3] \n"
" \n"
" tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
" it eq \n"
" vstmdbeq r0!, {s16-s31} \n"
" \n"
" stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
" \n"
" str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
" \n"
" stmdb sp!, {r3} \n"
" mov r0, %0 \n"
" msr basepri, r0 \n"
" dsb \n"
" isb \n"
" bl vTaskSwitchContext \n"
" mov r0, #0 \n"
" msr basepri, r0 \n"
" ldmia sp!, {r3} \n"
" \n"
" ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
" ldr r0, [r1] \n"
" \n"
" ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
" \n"
" tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
" it eq \n"
" vldmiaeq r0!, {s16-s31} \n"
" \n"
" msr psp, r0 \n"
" isb \n"
" \n"
#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
#if WORKAROUND_PMU_CM001 == 1
" push { r14 } \n"
" pop { pc } \n"
#endif
#endif
" \n"
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
);
}
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
/* The SysTick runs at the lowest interrupt priority, so when this interrupt
executes all interrupts must be unmasked. There is therefore no need to
save and then restore the interrupt mask value as its value is already
known. */
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
/* A context switch is required. Context switching is performed in
the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
}
portENABLE_INTERRUPTS();
}
/*-----------------------------------------------------------*/
#if configUSE_TICKLESS_IDLE == 1
__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
{
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
/* Stop the SysTick momentarily. The time the SysTick is stopped for
is accounted for as best it can be, but using the tickless mode will
inevitably result in some tiny drift of the time maintained by the
kernel with respect to calendar time. */
portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
/* Calculate the reload value required to wait xExpectedIdleTime
tick periods. -1 is used because this code will execute part way
through one of the tick periods. */
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
ulReloadValue -= ulStoppedTimerCompensation;
}
/* Enter a critical section but don't use the taskENTER_CRITICAL()
method as that will mask interrupts that should exit sleep mode. */
__asm volatile( "cpsid i" );
__asm volatile( "dsb" );
__asm volatile( "isb" );
/* If a context switch is pending or a task is waiting for the scheduler
to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
/* Restart from whatever is left in the count register to complete
this tick period. */
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
periods. */
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Re-enable interrupts - see comments above the cpsid instruction()
above. */
__asm volatile( "cpsie i" );
}
else
{
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
/* Clear the SysTick count flag and set the count value back to
zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
set its parameter to 0 to indicate that its implementation contains
its own wait for interrupt or wait for event instruction, and so wfi
should not be executed again. However, the original expected idle
time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
{
__asm volatile( "dsb" );
__asm volatile( "wfi" );
__asm volatile( "isb" );
}
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Stop SysTick. Again, the time the SysTick is stopped for is
accounted for as best it can be, but using the tickless mode will
inevitably result in some tiny drift of the time maintained by the
kernel with respect to calendar time. */
ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
/* Re-enable interrupts - see comments above the cpsid instruction()
above. */
__asm volatile( "cpsie i" );
if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
/* The tick interrupt has already executed, and the SysTick
count reloaded with ulReloadValue. Reset the
portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
underflowed because the post sleep hook did something
that took too long. */
if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
/* The tick interrupt handler will already have pended the tick
processing in the kernel. As the pending tick will be
processed as soon as this function exits, the tick value
maintained by the tick is stepped forward by one less than the
time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
/* Something other than the tick interrupt ended the sleep.
Work out how long the sleep lasted rounded to complete tick
periods (not the ulReload value which accounted for part
ticks). */
ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* How many complete tick periods passed while the processor
was waiting? */
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
/* The reload value is set to whatever fraction of a single tick
period remains. */
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
value. The critical section is used to ensure the tick interrupt
can only execute once in the case that the reload register is near
zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
portENTER_CRITICAL();
{
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
vTaskStepTick( ulCompleteTickPeriods );
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
}
portEXIT_CRITICAL();
}
}
#endif /* #if configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
/* Calculate the constants required to configure the tick interrupt. */
#if configUSE_TICKLESS_IDLE == 1
{
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vPortEnableVFP( void )
{
__asm volatile
(
" ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
" ldr r1, [r0] \n"
" \n"
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
" str r1, [r0] \n"
" bx r14 "
);
}
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
{
/* Look up the interrupt's priority. */
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
/* The following assertion will fail if a service routine (ISR) for
an interrupt that has been assigned a priority above
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
function. ISR safe FreeRTOS API functions must *only* be called
from interrupts that have been assigned a priority at or below
configMAX_SYSCALL_INTERRUPT_PRIORITY.
Numerically low interrupt priority numbers represent logically high
interrupt priorities, therefore the priority of the interrupt must
be set to a value equal to or numerically *higher* than
configMAX_SYSCALL_INTERRUPT_PRIORITY.
Interrupts that use the FreeRTOS API must not be left at their
default priority of zero as that is the highest possible priority,
which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
and therefore also guaranteed to be invalid.
FreeRTOS maintains separate thread and ISR API functions to ensure
interrupt entry is as fast and simple as possible.
The following links provide detailed information:
http://www.freertos.org/RTOS-Cortex-M3-M4.html
http://www.freertos.org/FAQHelp.html */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
/* Priority grouping: The interrupt controller (NVIC) allows the bits
that define each interrupt's priority to be split between bits that
define the interrupt's pre-emption priority bits and bits that define
the interrupt's sub-priority. For simplicity all bits must be defined
to be pre-emption priority bits. The following assertion will fail if
this is not the case (if some bits represent a sub-priority).
If the application only uses CMSIS libraries for interrupt
configuration then the correct setting can be achieved on all Cortex-M
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
scheduler. Note however that some vendor specific peripheral libraries
assume a non-zero priority group setting, in which cases using a value
of zero will result in unpredicable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
#endif /* configASSERT_DEFINED */

284
FreeRTOS/portable/GCC/ARM_CM4F/portmacro.h Normal file
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/*
FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE uint32_t
#define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t;
typedef unsigned long UBaseType_t;
#if( configUSE_16_BIT_TICKS == 1 )
typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff
#else
typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
#define portYIELD() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\
/* Barriers are normally not required but do ensure the code is completely \
within the specified behaviour for the architecture. */ \
__asm volatile( "dsb" ); \
__asm volatile( "isb" ); \
}
#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)
#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
#define portENABLE_INTERRUPTS() vPortSetBASEPRI(0)
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
not necessary for to use this port. They are defined so the common demo files
(which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
#ifndef portSUPPRESS_TICKS_AND_SLEEP
extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
#endif
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Generic helper function. */
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
{
uint8_t ucReturn;
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
return ucReturn;
}
/* Check the configuration. */
#if( configMAX_PRIORITIES > 32 )
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
#endif
/* Store/clear the ready priorities in a bit map. */
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
#ifdef configASSERT
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
/* portNOP() is not required by this port. */
#define portNOP()
#define portINLINE __inline
#ifndef portFORCE_INLINE
#define portFORCE_INLINE inline __attribute__(( always_inline))
#endif
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
if( ulCurrentInterrupt == 0 )
{
xReturn = pdFALSE;
}
else
{
xReturn = pdTRUE;
}
return xReturn;
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;
__asm volatile
(
" mov %0, %1 \n" \
" msr basepri, %0 \n" \
" isb \n" \
" dsb \n" \
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile
(
" mrs %0, basepri \n" \
" mov %1, %2 \n" \
" msr basepri, %1 \n" \
" isb \n" \
" dsb \n" \
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
/* This return will not be reached but is necessary to prevent compiler
warnings. */
return ulOriginalBASEPRI;
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue )
);
}
/*-----------------------------------------------------------*/
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */

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GCC_COMPAT/include/math.h Normal file
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#ifndef GCC_COMPAT_MATH_H
#define GCC_COMPAT_MATH_H
double sqrt(double value);
double pow(double base, double exponent);
double atan(double value);
double tan(double value);
#endif

15
GCC_COMPAT/include/stdio.h Normal file
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#ifndef GCC_COMPAT_STDIO_H
#define GCC_COMPAT_STDIO_H
#include <stdarg.h>
#include <stddef.h>
typedef struct __gcc_compat_file FILE;
int printf(const char *format, ...);
int sprintf(char *buffer, const char *format, ...);
int snprintf(char *buffer, size_t size, const char *format, ...);
int vsnprintf(char *buffer, size_t size, const char *format, va_list args);
int fputc(int ch, FILE *stream);
#endif

8
GCC_COMPAT/include/stdlib.h Normal file
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#ifndef GCC_COMPAT_STDLIB_H
#define GCC_COMPAT_STDLIB_H
#include <stddef.h>
int abs(int value);
#endif

12
GCC_COMPAT/include/string.h Normal file
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#ifndef GCC_COMPAT_STRING_H
#define GCC_COMPAT_STRING_H
#include <stddef.h>
void *memcpy(void *destination, const void *source, size_t count);
void *memset(void *destination, int value, size_t count);
int memcmp(const void *left, const void *right, size_t count);
size_t strlen(const char *string);
char *strcpy(char *destination, const char *source);
#endif

336
GCC_COMPAT/runtime.c Normal file
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#include "stm32f4xx.h"
#include <stdarg.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
typedef struct
{
char *buffer;
size_t capacity;
size_t length;
} OutputBuffer;
static void output_char(OutputBuffer *output, char value)
{
if (output->capacity != 0U && output->length + 1U < output->capacity)
{
output->buffer[output->length] = value;
}
output->length++;
}
static void output_unsigned(OutputBuffer *output, uint32_t value, unsigned int base,
unsigned int width, char pad, int uppercase)
{
char digits[16];
unsigned int count = 0U;
const char *alphabet = uppercase ? "0123456789ABCDEF" : "0123456789abcdef";
do
{
digits[count++] = alphabet[value % base];
value /= base;
} while (value != 0U);
while (count < width)
{
output_char(output, pad);
width--;
}
while (count != 0U)
{
output_char(output, digits[--count]);
}
}
int vsnprintf(char *buffer, size_t size, const char *format, va_list args)
{
OutputBuffer output = {buffer, size, 0U};
while (*format != '\0')
{
unsigned int width = 0U;
char pad = ' ';
int is_long = 0;
char specifier;
if (*format != '%')
{
output_char(&output, *format++);
continue;
}
format++;
if (*format == '%')
{
output_char(&output, *format++);
continue;
}
if (*format == '0')
{
pad = '0';
format++;
}
while (*format >= '0' && *format <= '9')
{
width = width * 10U + (unsigned int)(*format++ - '0');
}
if (*format == 'l')
{
is_long = 1;
format++;
}
specifier = *format++;
if (specifier == 's')
{
const char *text = va_arg(args, const char *);
if (text == NULL)
{
text = "(null)";
}
while (*text != '\0')
{
output_char(&output, *text++);
}
}
else if (specifier == 'c')
{
output_char(&output, (char)va_arg(args, int));
}
else if (specifier == 'd' || specifier == 'i')
{
int32_t value = is_long ? (int32_t)va_arg(args, long) : (int32_t)va_arg(args, int);
uint32_t magnitude;
if (value < 0)
{
output_char(&output, '-');
magnitude = 0U - (uint32_t)value;
if (width != 0U)
{
width--;
}
}
else
{
magnitude = (uint32_t)value;
}
output_unsigned(&output, magnitude, 10U, width, pad, 0);
}
else if (specifier == 'u' || specifier == 'x' || specifier == 'X')
{
uint32_t value = is_long ? (uint32_t)va_arg(args, unsigned long)
: (uint32_t)va_arg(args, unsigned int);
unsigned int base = specifier == 'u' ? 10U : 16U;
output_unsigned(&output, value, base, width, pad, specifier == 'X');
}
else if (specifier == 'p')
{
uintptr_t value = (uintptr_t)va_arg(args, void *);
output_char(&output, '0');
output_char(&output, 'x');
output_unsigned(&output, (uint32_t)value, 16U, 8U, '0', 0);
}
else
{
output_char(&output, '%');
output_char(&output, specifier);
}
}
if (output.capacity != 0U)
{
size_t terminator = output.length < output.capacity ? output.length : output.capacity - 1U;
output.buffer[terminator] = '\0';
}
return (int)output.length;
}
int snprintf(char *buffer, size_t size, const char *format, ...)
{
int result;
va_list args;
va_start(args, format);
result = vsnprintf(buffer, size, format, args);
va_end(args);
return result;
}
int sprintf(char *buffer, const char *format, ...)
{
int result;
va_list args;
va_start(args, format);
result = vsnprintf(buffer, (size_t)-1, format, args);
va_end(args);
return result;
}
int printf(const char *format, ...)
{
char buffer[192];
int result;
size_t count;
va_list args;
va_start(args, format);
result = vsnprintf(buffer, sizeof(buffer), format, args);
va_end(args);
count = result < 0 ? 0U : (size_t)result;
if (count >= sizeof(buffer))
{
count = sizeof(buffer) - 1U;
}
for (size_t index = 0U; index < count; index++)
{
while ((USART2->SR & USART_SR_TC) == 0U)
{
}
USART2->DR = (uint8_t)buffer[index];
}
return result;
}
void *memcpy(void *destination, const void *source, size_t count)
{
uint8_t *to = (uint8_t *)destination;
const uint8_t *from = (const uint8_t *)source;
while (count-- != 0U)
{
*to++ = *from++;
}
return destination;
}
void *memset(void *destination, int value, size_t count)
{
uint8_t *to = (uint8_t *)destination;
while (count-- != 0U)
{
*to++ = (uint8_t)value;
}
return destination;
}
int memcmp(const void *left, const void *right, size_t count)
{
const uint8_t *lhs = (const uint8_t *)left;
const uint8_t *rhs = (const uint8_t *)right;
while (count-- != 0U)
{
if (*lhs != *rhs)
{
return (int)*lhs - (int)*rhs;
}
lhs++;
rhs++;
}
return 0;
}
size_t strlen(const char *string)
{
const char *end = string;
while (*end != '\0')
{
end++;
}
return (size_t)(end - string);
}
char *strcpy(char *destination, const char *source)
{
char *result = destination;
do
{
*destination++ = *source;
} while (*source++ != '\0');
return result;
}
int abs(int value)
{
return value < 0 ? -value : value;
}
double sqrt(double value)
{
double estimate;
if (value <= 0.0)
{
return value == 0.0 ? 0.0 : (0.0 / 0.0);
}
estimate = value > 1.0 ? value : 1.0;
for (unsigned int iteration = 0U; iteration < 12U; iteration++)
{
estimate = 0.5 * (estimate + value / estimate);
}
return estimate;
}
double pow(double base, double exponent)
{
int power = (int)exponent;
unsigned int magnitude;
double result = 1.0;
if ((double)power != exponent)
{
return 0.0 / 0.0;
}
magnitude = power < 0 ? (unsigned int)(-power) : (unsigned int)power;
while (magnitude != 0U)
{
if ((magnitude & 1U) != 0U)
{
result *= base;
}
base *= base;
magnitude >>= 1U;
}
return power < 0 ? 1.0 / result : result;
}
double atan(double value)
{
const double half_pi = 1.5707963267948966;
const double quarter_pi = 0.7853981633974483;
double sign = 1.0;
double result;
if (value < 0.0)
{
value = -value;
sign = -1.0;
}
if (value > 1.0)
{
double reciprocal = 1.0 / value;
result = half_pi - reciprocal * (quarter_pi + 0.273 * (1.0 - reciprocal));
}
else
{
result = value * (quarter_pi + 0.273 * (1.0 - value));
}
return sign * result;
}
double tan(double value)
{
const double pi = 3.1415926535897932;
double squared;
double sine;
double cosine;
while (value > 1.5707963267948966)
{
value -= pi;
}
while (value < -1.5707963267948966)
{
value += pi;
}
squared = value * value;
sine = value * (1.0 + squared * (-1.0 / 6.0 + squared * (1.0 / 120.0 +
squared * (-1.0 / 5040.0 + squared * (1.0 / 362880.0)))));
cosine = 1.0 + squared * (-1.0 / 2.0 + squared * (1.0 / 24.0 +
squared * (-1.0 / 720.0 + squared * (1.0 / 40320.0))));
return sine / cosine;
}

21
GCC_COMPAT/sys_gcc.c Normal file
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@@ -0,0 +1,21 @@
#include "sys.h"
void WFI_SET(void)
{
__WFI();
}
void INTX_DISABLE(void)
{
__disable_irq();
}
void INTX_ENABLE(void)
{
__enable_irq();
}
void MSR_MSP(u32 address)
{
__set_MSP(address);
}

125
Makefile Normal file
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@@ -0,0 +1,125 @@
PROJECT := OriginCar
BUILD ?= debug
FRAMEWORK_DIR ?= ../../stm32/stm32f407-gcc-framework
FRAMEWORK_DIR := $(abspath $(FRAMEWORK_DIR))
CC := arm-none-eabi-gcc
OBJCOPY := arm-none-eabi-objcopy
SIZE := arm-none-eabi-size
NM := arm-none-eabi-nm
OPENOCD := openocd
MCU := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard
DEFS := -DSTM32F40_41xxx -DUSE_STDPERIPH_DRIVER -DARM_MATH_CM4 \
-D__FPU_PRESENT=1 -D__FPU_USED=1 -DHSE_VALUE=8000000U
INCLUDES := \
-IGCC_COMPAT/include \
-IUSER -ICORE -IFWLIB/inc \
-ISYSTEM/delay -ISYSTEM/sys -ISYSTEM/usart \
-IHARDWARE -IHARDWARE/MPU6050 -IBALANCE \
-IFreeRTOS/include -IFreeRTOS/portable/GCC/ARM_CM4F
APP_SRC := \
USER/main.c USER/stm32f4xx_it.c USER/system_stm32f4xx.c \
HARDWARE/adc.c HARDWARE/can.c HARDWARE/encoder.c HARDWARE/key.c \
HARDWARE/motor.c HARDWARE/oled.c HARDWARE/pstwo.c HARDWARE/timer.c \
HARDWARE/usartx.c HARDWARE/MPU6050/MPU6050.c HARDWARE/MPU6050/I2C.c \
SYSTEM/delay/delay.c SYSTEM/usart/usart.c \
BALANCE/system.c BALANCE/balance.c BALANCE/robot_select_init.c BALANCE/show.c
FWLIB_SRC := \
FWLIB/src/misc.c FWLIB/src/stm32f4xx_gpio.c FWLIB/src/stm32f4xx_rcc.c \
FWLIB/src/stm32f4xx_syscfg.c FWLIB/src/stm32f4xx_usart.c \
FWLIB/src/stm32f4xx_adc.c FWLIB/src/stm32f4xx_can.c \
FWLIB/src/stm32f4xx_tim.c FWLIB/src/stm32f4xx_pwr.c
FREERTOS_SRC := \
FreeRTOS/croutine.c FreeRTOS/event_groups.c FreeRTOS/list.c \
FreeRTOS/queue.c FreeRTOS/tasks.c FreeRTOS/timers.c \
FreeRTOS/portable/GCC/ARM_CM4F/port.c \
FreeRTOS/portable/MemMang/heap_4.c
C_SRC := $(APP_SRC) $(FWLIB_SRC) $(FREERTOS_SRC) \
GCC_COMPAT/runtime.c GCC_COMPAT/sys_gcc.c
UPPER_C_SRC := HARDWARE/LED.C
BUILD_DIR := build/$(BUILD)
C_OBJS := $(addprefix $(BUILD_DIR)/,$(C_SRC:.c=.o))
UPPER_C_OBJS := $(addprefix $(BUILD_DIR)/,$(UPPER_C_SRC:.C=.o))
STARTUP_OBJ := $(BUILD_DIR)/startup_stm32f407xx_gcc.o
OBJS := $(C_OBJS) $(UPPER_C_OBJS) $(STARTUP_OBJ)
DEPS := $(OBJS:.o=.d)
ifeq ($(BUILD),release)
OPT_FLAGS := -Os -g0 -DNDEBUG
else
OPT_FLAGS := -O0 -g3 -DDEBUG -fno-omit-frame-pointer
endif
CFLAGS := $(MCU) $(DEFS) $(INCLUDES) $(OPT_FLAGS) \
-std=gnu11 -ffreestanding -ffunction-sections -fdata-sections -fno-common \
-Wall -Wextra -Wshadow -Wno-unused-parameter -Wno-sign-compare \
-MMD -MP
ASFLAGS := $(MCU) $(DEFS) $(OPT_FLAGS) -x assembler-with-cpp -Wa,--gdwarf-2
LDSCRIPT := $(FRAMEWORK_DIR)/STM32F407VGTX_FLASH.ld
LDFLAGS := $(MCU) -nostdlib -T$(LDSCRIPT) \
-Wl,-Map=$(BUILD_DIR)/$(PROJECT).map,--cref,--gc-sections \
-Wl,--start-group -lgcc -Wl,--end-group
ELF := $(BUILD_DIR)/$(PROJECT).elf
HEX := $(BUILD_DIR)/$(PROJECT).hex
BIN := $(BUILD_DIR)/$(PROJECT).bin
.PHONY: all debug release clean flash debug-server linkscope-info check-tools
all: check-tools $(ELF) $(HEX) $(BIN)
$(SIZE) $(ELF)
debug:
$(MAKE) BUILD=debug all
release:
$(MAKE) BUILD=release all
check-tools:
@command -v $(CC) >/dev/null || { echo "Missing $(CC)"; exit 1; }
@command -v $(OPENOCD) >/dev/null || { echo "Missing $(OPENOCD)"; exit 1; }
@test -f $(LDSCRIPT) || { echo "Framework not found: $(FRAMEWORK_DIR)"; exit 1; }
$(ELF): $(OBJS)
@mkdir -p $(dir $@)
$(CC) $(OBJS) $(LDFLAGS) -o $@
$(HEX): $(ELF)
$(OBJCOPY) -O ihex $< $@
$(BIN): $(ELF)
$(OBJCOPY) -O binary $< $@
$(BUILD_DIR)/%.o: %.c
@mkdir -p $(dir $@)
$(CC) $(CFLAGS) -c $< -o $@
$(BUILD_DIR)/%.o: %.C
@mkdir -p $(dir $@)
$(CC) $(CFLAGS) -x c -c $< -o $@
$(STARTUP_OBJ): $(FRAMEWORK_DIR)/CORE/startup_stm32f407xx_gcc.s
@mkdir -p $(dir $@)
$(CC) $(ASFLAGS) -c $< -o $@
flash: all
$(OPENOCD) -f openocd.cfg -c "program $(ELF) verify reset exit"
debug-server:
$(OPENOCD) -f openocd.cfg
linkscope-info: $(ELF)
@echo "ELF: $(abspath $(ELF))"
@echo "GDB server: localhost:3333 (run 'make debug-server')"
@echo "Example observable globals:"
@$(NM) -S --size-sort $(ELF) | grep -E ' (Car_Mode|RC_Velocity|Velocity_KP|Velocity_KI|Move_X|Move_Y|Move_Z)$$' || true
clean:
rm -rf build
-include $(DEPS)

23
README_GCC.md Normal file
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# OriginCar GCC build
This keeps the original Keil project intact and adds an ARM GCC build for the
STM32F407ZG. It reuses the GCC startup file, linker script, SVD and OpenOCD
tooling from ../../stm32/stm32f407-gcc-framework.
## Commands
make -j8 # debug ELF/HEX/BIN with -O0 -g3
make release # size-optimized release build
make flash # build, program, verify and reset through DAPLink
make debug-server # OpenOCD on localhost:3333
make linkscope-info # print the ELF path and observable globals
The LinkScope symbol file is build/debug/OriginCar.elf. Start OpenOCD with
make debug-server, then select external OpenOCD in LinkScope and connect to
localhost:3333. The OpenOCD target accepts four GDB connections so VS Code
Cortex-Debug and LinkScope can share it.
The Homebrew cross compiler has no newlib, so GCC_COMPAT supplies the small C
runtime surface used by this legacy project. Its printf supports integer,
string, character, hexadecimal and pointer formats; floating-point formatting
is intentionally not included.

2
SYSTEM/usart/usart.c
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@@ -8,7 +8,7 @@
//////////////////////////////////////////////////////////////////
//加入以下代码,支持printf函数,而不需要选择use MicroLIB
#if 1
#if defined(__CC_ARM)
#pragma import(__use_no_semihosting)
//标准库需要的支持函数
struct __FILE

8
openocd.cfg Normal file
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@@ -0,0 +1,8 @@
source [find interface/cmsis-dap.cfg]
transport select swd
source [find target/stm32f4x.cfg]
adapter speed 5000
reset_config srst_only srst_nogate
gdb_port 3333
$_TARGETNAME configure -gdb-max-connections 4